Hardware & Virtual Machines
RISC/CISC · Parallel Architectures · Boolean Algebra · Karnaugh Maps
| Feature | RISC (Reduced Instruction Set) | CISC (Complex Instruction Set) |
|---|---|---|
| Instructions | Small, simple set (~100) | Large, complex set (hundreds) |
| Clock cycles per instr. | Usually 1 | Multiple (1–20+) |
| Registers | Many general-purpose registers | Fewer registers |
| Memory access | Load/Store only (register-based ops) | Instructions can access memory directly |
| Pipelining | ✅ Highly efficient | ⚠️ Harder due to variable instruction length |
| Compiler complexity | Higher — more instructions needed | Lower — single instruction does more |
| Examples | ARM (mobile chips), MIPS | Intel x86, AMD |
RISC processors achieve speed through pipelining — while one instruction is being executed, the next is being decoded, and the one after that is being fetched. Multiple instructions in flight simultaneously.
Instr 1
Instr 1
Instr 1
Instr 1
Instr 2
Instr 2
Instr 2
Instr 2
SISD — Single Instruction, Single Data
Classic sequential processor. One instruction at a time on one data stream. Traditional Von Neumann architecture.
SIMD — Single Instruction, Multiple Data
Same operation applied to multiple data items simultaneously. Great for graphics, audio processing, AI matrix operations.
MISD — Multiple Instruction, Single Data
Multiple processors each run different instructions on the same data stream. Rare — used in fault-tolerant systems (e.g. flight control computers running redundant checks).
MIMD — Multiple Instruction, Multiple Data
Multiple processors, each with their own instructions and data. Most modern multi-core CPUs. Most flexible parallel architecture.
✅ Benefits of VMs
- Run multiple OS on one machine
- Isolation — crash in VM doesn’t affect host
- Testing software safely
- Cloud computing infrastructure
- Easy backup (snapshot the VM)
❌ Limitations of VMs
- Performance overhead vs bare metal
- Requires significant RAM/storage
- Hardware access may be limited or emulated
Adds two bits A and B. Outputs: Sum and Carry.
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
A full adder adds bits A, B, and a Carry-In (Cin) from the previous stage. Used to build multi-bit adders.
then Half Adder(Sum₁, Cin) → Sum, C₂
Final Carry = C₁ OR C₂
Flip-flops are circuits that store a single bit. They are the building blocks of registers and RAM.
Two inputs: S (Set) and R (Reset). Output: Q (and Q̄).
| S | R | Q (next) | State |
|---|---|---|---|
| 0 | 0 | Q (unchanged) | Hold |
| 1 | 0 | 1 | Set |
| 0 | 1 | 0 | Reset |
| 1 | 1 | INVALID | ⚠️ Forbidden |
| J | K | Q (next) | State |
|---|---|---|---|
| 0 | 0 | Q (unchanged) | Hold |
| 1 | 0 | 1 | Set |
| 0 | 1 | 0 | Reset |
| 1 | 1 | NOT Q | ✅ Toggle! |
J=1, K=1 now means toggle — output flips. This eliminates the forbidden state and makes the JK flip-flop the most commonly used type.
De Morgan’s laws let you simplify or transform Boolean expressions by swapping AND/OR and inverting:
Law 1
Law 2
A K-map is a visual tool for simplifying Boolean expressions. You group 1s in powers of 2 to eliminate variables.
Given: F(A,B,C) = Σm(1,3,5,7) — minterms where F=1
- Groups must be 1, 2, 4, or 8 cells (powers of 2)
- Groups must be rectangular (can wrap around edges)
- Use the largest possible groups
- Each 1 must be in at least one group
- Each variable that changes within a group is eliminated
- Know RISC vs CISC differences — especially pipelining advantage
- Name and describe all 4 Flynn architectures with examples
- Draw truth tables for half adder and full adder
- SR vs JK flip-flop — know the forbidden state fix
- Apply De Morgan’s laws to simplify expressions
- Solve 2-variable and 3-variable K-maps
- State benefits AND limitations of virtual machines
