Chapter 4: Processor Fundamentals – 9618 CS AS Level Notes

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Chapter 4 · Paper 1

Processor Fundamentals

The Von Neumann model, CPU architecture, registers, the Fetch-Execute cycle, assembly language, addressing modes and bit manipulation.

4.1 CPU Architecture 4.2 Assembly Language 4.3 Bit Manipulation

4.1 Central Processing Unit (CPU) Architecture

Von Neumann Model

Von Neumann Architecture

A computer architecture where both program instructions and data are stored in the same memory using the same address space. The CPU fetches instructions from memory and executes them sequentially. This is the foundation of virtually all modern computers.

Stored Program Concept: Programs are stored as binary data in memory just like any other data. This means programs can be loaded and changed without modifying hardware — unlike early fixed-program computers.

Control Unit (CU)

Fetches, decodes instructions. Controls all other components via control signals. Manages the Fetch-Execute cycle.

Arithmetic & Logic Unit (ALU)

Performs arithmetic (+, −, ×, ÷) and logical operations (AND, OR, NOT, comparisons). Results stored in ACC.

Registers

Ultra-fast storage inside CPU: PC, MAR, MDR, ACC, CIR, IX, Status Register, General Purpose

System Buses → Main Memory (IAS)

Address Bus | Data Bus | Control Bus — connect CPU to RAM and other components

Special Purpose Registers

Register	Full Name	Purpose
PC	Program Counter	Holds address of the NEXT instruction to be fetched
MAR	Memory Address Register	Holds address being read from or written to in memory
MDR	Memory Data Register	Holds data read from or about to be written to memory
ACC	Accumulator	General purpose register; holds results of ALU operations
CIR	Current Instruction Register	Holds the instruction currently being decoded and executed
IX	Index Register	Used in indexed addressing — added to base address
Status	Status/Flag Register	Bits indicate: overflow, carry, zero, negative, interrupt

System Buses

Bus	Direction	Carries	Width Effect
Address Bus	CPU → Memory (unidirectional)	Memory address to read/write	More bits → can address more memory
Data Bus	Bidirectional	Actual data being transferred	Wider = more data per transfer
Control Bus	Bidirectional	Control signals (read/write, clock, interrupt)	More lines = more control signals

Performance Factors

Factor	How It Improves Performance
Clock Speed (GHz)	Higher clock → more cycles per second → more instructions executed per second
Number of Cores	Multiple cores can execute different threads simultaneously (true parallelism)
Bus Width	Wider data bus transfers more bits per cycle
Cache Memory	Very fast SRAM between CPU and RAM. L1 (fastest, smallest) → L2 → L3. Reduces RAM access time.
Processor Type	RISC vs CISC architecture (covered at A Level)

The Fetch-Execute (F-E) Cycle

Animated Fetch-Execute Cycle

FETCH 1: MAR ← [PC] — copy contents of PC into MAR

FETCH 2: MDR ← [MAR], PC ← PC + 1 — fetch instruction from memory; increment PC

DECODE: CIR ← [MDR] — copy instruction to CIR; CU decodes opcode and operand

EXECUTE: CU sends control signals to relevant component (ALU, memory, etc.)

LOOP: Return to Fetch — PC now holds address of next instruction → repeat

    Register Transfer Notation
Fetch:
  MAR ← [PC]           // MAR gets address from PC
  MDR ← [[MAR]]        // MDR gets data from memory at that address
  PC  ← [PC] + 1       // Increment PC to point to next instruction
  CIR ← [MDR]          // CIR gets the fetched instruction

Execute (e.g. ADD 50):
  MAR ← [CIR(operand)] // Get operand address
  MDR ← [[MAR]]        // Fetch operand value from memory
  ACC ← [ACC] + [MDR]  // ALU adds value to ACC
  

Interrupts

Interrupt

An interrupt is a signal sent to the CPU requesting it to stop its current task and attend to a higher-priority event. The CPU checks for interrupts at the end of each F-E cycle.

Category	Examples
Hardware interrupt	Keyboard keypress, mouse click, printer finished, network data arrived
Software interrupt	Division by zero, program requesting OS service
Timer interrupt	Scheduling — allows OS to switch between processes

Interrupt Handling Process

1. CPU finishes current instruction → 2. Checks interrupt flag → 3. If interrupt pending: saves current state to stack (PC, registers) → 4. Loads address of Interrupt Service Routine (ISR) into PC → 5. ISR executes → 6. Restores saved state → 7. Resumes original program.

4.2 Assembly Language

Assembly language is a low-level language with a direct one-to-one relationship with machine code. Each assembly instruction corresponds to one machine code instruction.

Two-Pass Assembler

Why Two Passes?

An assembler translates assembly code to machine code. Two passes are needed because a program may jump forward to a label that hasn't been defined yet (forward reference).

Pass	What It Does
Pass 1	Reads all instructions. Builds a symbol table mapping all label names to their memory addresses.
Pass 2	Translates each instruction to binary. Uses the symbol table to resolve all label references.

Addressing Modes

Mode	Operand Means…	Example	Use Case
Immediate	The value itself (not an address)	`LDM #42` → ACC = 42	Load a known constant
Direct	The address in memory	`LDD 200` → ACC = Memory[200]	Access a variable
Indirect	Address contains another address	`LDI 200` → ACC = Memory[Memory[200]]	Pointer dereferencing
Indexed	Address + IX register content	`LDX 200` → ACC = Memory[200+IX]	Array access in loops
Relative	Offset from current PC value	`JMP +3` → skip 3 instructions	Relative jumps

Instruction Set Reference

Opcode	Operand	Operation
LDM	#n	Load immediate value n into ACC
LDD	<addr>	Load contents of memory address into ACC
LDI	<addr>	Indirect: load from address stored at address
LDX	<addr>	Indexed: load from address + IX
LDR	#n	Load immediate value n into IX
STO	<addr>	Store ACC contents to memory address
ADD	<addr> / #n	Add value to ACC
SUB	<addr> / #n	Subtract value from ACC
INC	ACC or IX	Increment register by 1
DEC	ACC or IX	Decrement register by 1
JMP	<addr>	Unconditional jump to address
CMP	<addr> / #n	Compare ACC with value (sets flags)
JPE	<addr>	Jump if previous compare was equal
JPN	<addr>	Jump if previous compare was NOT equal
IN	—	Read character from keyboard; store ASCII in ACC
OUT	—	Output character with ASCII value in ACC to screen
END	—	Return control to OS

    Assembly Trace Example
; Program adds two numbers stored at memory locations x and y
        LDM  #0        ; ACC = 0
        ADD  x         ; ACC = ACC + memory[x] = 0 + 5 = 5
        ADD  y         ; ACC = ACC + memory[y] = 5 + 3 = 8
        STO  result    ; memory[result] = 8
        END

x:      5              ; data declaration
y:      3
result: 0
  

4.3 Bit Manipulation

Binary Shifts

Shift Type	Description	Left Shift Effect	Right Shift Effect
Logical Shift	Bits shift; zeros fill vacated positions; bits shifted out are lost	×2 (approximately)	÷2 (unsigned)
Arithmetic Shift	Like logical but right shift preserves sign bit (MSB)	×2	÷2 (preserves sign)
Cyclic Shift	Bits wrap around — shifted-out bit re-enters the other end	Rotate left	Rotate right

    Shift Example
; Logical Left Shift by 2 (using LSL #2)
Before: 0 0 0 0 1 1 0 1  = 13
After:  0 0 1 1 0 1 0 0  = 52  (13 × 4)

; Logical Right Shift by 1 (using LSR #1)
Before: 0 0 1 0 1 1 0 0  = 44
After:  0 0 0 1 0 1 1 0  = 22  (44 ÷ 2)
  

Bit Masking

Bit masking uses logical operations (AND, OR, XOR) to manipulate specific bits while leaving others unchanged.

Operation	Mask Bit	Effect on Target Bit	Purpose
AND with 0	0	Forces bit to 0 (CLEAR)	Clear specific bits
AND with 1	1	Preserves the bit (TEST)	Test if bit is set
OR with 1	1	Forces bit to 1 (SET)	Set specific bits
XOR with 1	1	Flips the bit (TOGGLE)	Toggle specific bits

    Bit Masking — Testing and Setting
; TEST if bit 3 (0-indexed from right) is set in ACC
        AND  B00001000   ; mask: only keep bit 3
        CMP  #0
        JPE  bit_clear   ; if result is 0, bit was 0
                         ; if result is not 0, bit was 1

; SET bit 5 in ACC
        OR   B00100000   ; forces bit 5 to 1, all others unchanged

; CLEAR bit 2 in ACC
        AND  B11111011   ; mask: bit 2 = 0, all others = 1
  

Assembly Instructions for Bit Operations

Instruction	Operation
`AND #n / Bn / &n`	Bitwise AND of ACC with operand
`OR #n / Bn / &n`	Bitwise OR of ACC with operand
`XOR #n / Bn / &n`	Bitwise XOR of ACC with operand
`LSL #n`	Logical shift ACC left by n bits; zeros fill right
`LSR #n`	Logical shift ACC right by n bits; zeros fill left

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