Chapter 4 – Processor Fundamentals

1. Central Processing Unit (CPU) Architecture

Exam Focus:

• Von Neumann vs. Harvard architecture (differences, advantages).
• Roles of registers (MAR, MDR, PC, ACC, CIR, IX).
• Fetch-Execute Cycle (RTN notation, interrupts).

Theory:

• Von Neumann Model: Single bus for data/instructions; bottleneck issue.
• Registers:
  • MAR: Holds memory address for read/write.
  • MDR: Temporarily stores data fetched from memory.
  • PC: Points to next instruction.
  • ACC: Stores ALU results.
• Interrupts: Priority handling, ISR (Interrupt Service Routine).

Practice:

1. Describe the role of the MAR and MDR during the fetch-execute cycle.
   • Memory Address Register (MAR):
     • Holds the address of the next instruction or data to be fetched from memory.
     • During the fetch stage, the address from the Program Counter (PC) is copied into the MAR.
   • Memory Data Register (MDR):
     • Temporarily stores the data or instruction fetched from memory.
     • After the MAR provides the address, the CPU retrieves the contents of that memory location and stores it in the MDR.
     • The instruction/data is then transferred to the Current Instruction Register (CIR) for decoding.
2. Convert RTN to steps: MAR ← [PC], MDR ← [[MAR]], CIR ← [MDR].
   • MAR ← [PC]
     • The address of the next instruction (stored in the PC) is copied into the MAR.
     • Example: If PC = 100, then MAR = 100.
   • MDR ← [[MAR]]
     • The CPU fetches the instruction/data stored at the memory address held in the MAR and loads it into the MDR.
     • Example: If memory location 100 contains LDM #5, then MDR = LDM #5.
   • CIR ← [MDR]
     • The instruction in the MDR is transferred to the CIR for decoding and execution.
     • Example: CIR = LDM #5.

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2. Assembly Language & Addressing Modes

Exam Focus:

• Opcodes (LDM, STO, ADD, JMP).
• Addressing modes (immediate, direct, indirect, indexed).
• Trace tables (common in exams).

Theory:

• Addressing Modes:
  • Immediate: Operand = actual data (e.g., LDM #5).
  • Direct: Operand = memory address (e.g., LDD 100).
  • Indexed: LDX 100 uses [100 + IX].
• Branching: Conditional (JPE/JPN) vs. unconditional (JMP).

Practice:

1. Translate to machine steps:
   • LDM #10
   • ADD 200
   • STO 201
   • Answer: Loads 10 in the accumulator, adds data from memory location 200 and stores it into memory location 201.
2. Complete a trace table for:
   • LDM #3
   • STO 100
   • INC ACC
   • Answer: Loads 3 in the accumulator, stores it in memory location 100(stores 3 in that location). increments accumulator making the acccumulator contents “4”.

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3. Bit Manipulation

Exam Focus:

• Logical shifts (LSL/LSR) vs. arithmetic shifts.
• Bit masking (AND/OR/XOR for testing/setting bits).

Theory:

• Shifts:
  • LSL #2 = multiply by 4 (e.g., 00001100 → 00110000).
  • LSR #1 = divide by 2 (e.g., 00001100 → 00000110).
• Masking:
  • Test bit 3: AND #8 (binary 00001000).
  • Set bits 4-7 to 0: AND #15 (binary 00001111).

Practice:

1. Perform LSL #3 on 00010110 and state the denary result.
   • Binary before shift: 00010110 (22 in denary).
   • After LSL #3: 10110000 (shift left 3 places, fill with 0s).
   • Denary result: 10110000 = 176.
2. Write assembly to test if bit 5 is set in address 300.

The JPE statement wasn’t needed!

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4. System Performance Factors

Exam Focus:

• Clock speed, cache size, cores, bus width.

Theory:

• Clock Speed: Higher = more cycles/second.
• Cache: L1 (fastest), L2, L3 (shared); reduces “wait states.”
• Cores: Parallel processing (multithreading).

Practice:
Explain how increasing cache size improves performance.

Increasing cache size improves performance by reducing the number of cache misses, allowing the CPU to access frequently used data faster. This decreases idle time and increases instruction throughput.

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5. Exam-Style Questions

1. Short Answer:
   • Why does the Von Neumann model use a single bus? What is the drawback?
   • *Convert -42 to 8-bit two’s complement.*
2. Structured:
   • Trace this assembly program
     • LDM #5
     • ADD #3
     • STO 100
3. Essay:
   • Compare immediate and indexed addressing, with examples.

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6. Practical Applications

• AI in Processors: Predictive caching, branch prediction.
• Embedded Systems: Real-time interrupt handling (e.g., traffic lights).

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7. Embedded Systems

Definition:
Specialized computer systems designed to perform dedicated tasks (e.g., traffic lights, washing machines).

Key Features:

• Real-time operation: Must respond to inputs within strict deadlines.
• Limited resources: Small memory, low-power processors.
• Deterministic behavior: Predictable timing for critical tasks.

Examples:

• Medical devices (pacemakers).
• Automotive systems (ABS, airbag control).
• IoT devices (smart thermostats).

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8. Interrupt Handling in Embedded Systems

What is an Interrupt?
A signal from hardware/software that pauses the CPU’s current task to handle a high-priority event.

Why Use Interrupts?

• Efficiency: Avoids wasteful polling (e.g., constantly checking if a button is pressed).
• Timeliness: Critical events (e.g., sensor alarms) get immediate attention.

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Interrupt Handling Process

1. Interrupt Triggered
   • Hardware (e.g., timer overflow) or software (e.g., divide-by-zero) sends an interrupt request (IRQ).
2. CPU Response
   • Finishes current instruction, saves state (registers, PC) to the stack.
3. Jump to ISR
   • CPU loads the Interrupt Service Routine (ISR) address from the interrupt vector table.
4. Execute ISR
   • ISR handles the event (e.g., reads sensor data, turns on LED).
   • Must be short to avoid delaying other interrupts.
5. Return to Main Program
   • CPU restores saved state from the stack and resumes where it left off.

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Types of Interrupts

1. Hardware Interrupts
   • External (e.g., button press, UART data received).
   • Internal (e.g., timer overflow, ADC conversion complete).
2. Software Interrupts
   • Triggered by instructions (e.g., SWI in ARM).
   • Used for system calls (e.g., OS tasks).